74LV74PW,118
ActiveFLIP-FLOP, COMPLEMENTARY OUTPUT, POSITIVE EDGE, 74LV74, D, 100 MHZ, 25 MA, TSSOP
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74LV74PW,118
ActiveFLIP-FLOP, COMPLEMENTARY OUTPUT, POSITIVE EDGE, 74LV74, D, 100 MHZ, 25 MA, TSSOP
Technical Specifications
Parameters and characteristics for this part
| Specification | 74LV74PW,118 |
|---|---|
| Clock Frequency | 110 MHz |
| Current - Output High, Low [custom] | 12 mA |
| Current - Output High, Low [custom] | 12 mA |
| Current - Quiescent (Iq) | 80 µA |
| Function | Set(Preset) and Reset |
| Input Capacitance | 3.5 pF |
| Max Propagation Delay @ V, Max CL | 17 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Complementary |
| Package / Case | 14-TSSOP |
| Package / Case [x] | 0.173 ", 4.4 mm |
| Supplier Device Package | 14-TSSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 1 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 1170 | $ 0.36 | |
Description
General part information
74LV74PW Series
The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQoutputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.
Documents
Technical documentation and resources