Specification	74HC175D-Q100J

Clock Frequency	89 MHz
Current - Output High, Low [custom]	5.2 mA
Current - Output High, Low [custom]	5.2 mA
Current - Quiescent (Iq)	8 ÁA
Grade	Automotive
Input Capacitance	3.5 pF
Max Propagation Delay @ V, Max CL	30 ns
Mounting Type	Surface Mount
Number of Bits per Element	4
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	16-SOIC
Package / Case	0.154 in, 3.9 mm
Qualification	AEC-Q100
Supplier Device Package	16-SO
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

74HC175D-Q100 Series

Quad D-type flip-flop with reset; positive-edge trigger

Part	Trigger Type	Number of Elements	Max Propagation Delay @ V, Max CL	Current - Quiescent (Iq)	Supplier Device Package	Output Type	Input Capacitance	Clock Frequency	Qualification	Package / Case	Package / Case	Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Grade	Operating Temperature [Max]	Operating Temperature [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Mounting Type	Number of Bits per Element
Nexperia USA Inc. 74HC175D-Q100J	Positive Edge	1	30 ns	8 ÁA	16-SO	Complementary	3.5 pF	89 MHz	AEC-Q100	16-SOIC	0.154 in 3.9 mm	D-Type	6 V	2 V	Automotive	125 °C	-40 °C	5.2 mA	5.2 mA	Surface Mount	4

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	N/A	0	$ 0.27

Description

General part information

74HC175D-Q100 Series

The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and both Qn andQn outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW onMRcauses the flip-flops and outputs to be reset LOW.