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56-TSSOP
Integrated Circuits (ICs)

SN74LVT16543DGGR

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Texas Instruments

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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56-TSSOP
Integrated Circuits (ICs)

SN74LVT16543DGGR

Active
Texas Instruments

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVT16543DGGR
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]32 mA
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output Type3-State
Package / Case6.1 mm
Package / Case0.24 in
Package / Case56-TFSOP
Supplier Device Package56-TSSOP
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]2.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 6.98
Digi-Reel® 1$ 6.98
Tape & Reel (TR) 2000$ 3.81
Texas InstrumentsLARGE T&R 1$ 5.34
100$ 4.36
250$ 3.42
1000$ 2.90

Description

General part information

SN74LVT16543 Series

The 'LVT16543 are 16-bit registered transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (or) and output-enable (or) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable () input must be low in order to enter data from A or to output data from B. Ifis low andis low, the A-to-B latches are transparent; a subsequent low-to-high transition ofputs the A latches in the storage mode. Withandboth low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the,, andinputs.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.