SN74LV273AQWRKSRQ1
ActiveAUTOMOTIVE OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
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SN74LV273AQWRKSRQ1
ActiveAUTOMOTIVE OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LV273AQWRKSRQ1 |
|---|---|
| Clock Frequency | 160 MHz |
| Current - Output High, Low [custom] | 12 mA |
| Current - Output High, Low [custom] | 12 mA |
| Current - Quiescent (Iq) | 20 çA |
| Input Capacitance | 2 pF |
| Max Propagation Delay @ V, Max CL | 11 ns |
| Mounting Type | Wettable Flank, Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Push-Pull |
| Package / Case | 20-VFQFN Exposed Pad |
| Supplier Device Package | 20-VQFN (2.5x4.5) |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.92 | |
| 10 | $ 0.82 | |||
| 25 | $ 0.78 | |||
| 100 | $ 0.64 | |||
| 250 | $ 0.60 | |||
| 500 | $ 0.53 | |||
| 1000 | $ 0.42 | |||
| Digi-Reel® | 1 | $ 0.92 | ||
| 10 | $ 0.82 | |||
| 25 | $ 0.78 | |||
| 100 | $ 0.64 | |||
| 250 | $ 0.60 | |||
| 500 | $ 0.53 | |||
| 1000 | $ 0.42 | |||
| Tape & Reel (TR) | 3000 | $ 0.39 | ||
| 6000 | $ 0.37 | |||
| 9000 | $ 0.38 | |||
| 15000 | $ 0.36 | |||
| 21000 | $ 0.37 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.68 | |
| 100 | $ 0.52 | |||
| 250 | $ 0.39 | |||
| 1000 | $ 0.28 | |||
Description
General part information
SN74LV273A-Q1 Series
The SN74LV273A-Q1 device is an octal positive-edge triggered D-type flip-flop with shared direct active low clear (CLR)input and clock (CLK).
Information at the data (D) inputs meeting the setup time requirements is transferred to the (Q) outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level or transitioning from a high level to a low level, the D input has no effect at the output. Information at the data (Q) outputs can be asynchronously cleared with a low level input through the clear (CLR) pin.
The SN74LV273A-Q1 device is an octal positive-edge triggered D-type flip-flop with shared direct active low clear (CLR)input and clock (CLK).
Documents
Technical documentation and resources