LMK03002CISQ/NOPB
Active1566 TO 1724-MHZ, 800-FS RMS JITTER, PRECISION CLOCK CONDITIONER WITH INTEGRATED VCO
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LMK03002CISQ/NOPB
Active1566 TO 1724-MHZ, 800-FS RMS JITTER, PRECISION CLOCK CONDITIONER WITH INTEGRATED VCO
Technical Specifications
Parameters and characteristics for this part
| Specification | LMK03002CISQ/NOPB |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Divider/Multiplier | Yes/No |
| Frequency - Max [Max] | 1.724 GHz |
| Input | LVDS, LVCMOS, LVPECL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVPECL |
| Package / Case | 48-WFQFN Exposed Pad |
| PLL | True |
| Ratio - Input:Output | 1:4 |
| Supplier Device Package | 48-WQFN (7x7) |
| Type | Clock Conditioner |
| Voltage - Supply [Max] | 3.45 V |
| Voltage - Supply [Min] | 3.15 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 24.02 | |
| 10 | $ 22.15 | |||
| 25 | $ 21.15 | |||
| 100 | $ 18.91 | |||
| Digi-Reel® | 1 | $ 24.02 | ||
| 10 | $ 22.15 | |||
| 25 | $ 21.15 | |||
| 100 | $ 18.91 | |||
| Tape & Reel (TR) | 250 | $ 10.56 | ||
| Texas Instruments | SMALL T&R | 1 | $ 20.45 | |
| 100 | $ 17.86 | |||
| 250 | $ 13.77 | |||
| 1000 | $ 12.32 | |||
Description
General part information
LMK03002 Series
The LMK03002/LMK03002C precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and four LVPECL clock output distribution blocks.
The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Divider to feed the various clock distribution blocks.
Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to four system components.
Documents
Technical documentation and resources