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Integrated Circuits (ICs)

TPIC6B273DWR

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Texas Instruments

OCTAL D-TYPE LATCH WITH 150MA/CH

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SOIC (DW)
Integrated Circuits (ICs)

TPIC6B273DWR

Active
Texas Instruments

OCTAL D-TYPE LATCH WITH 150MA/CH

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationTPIC6B273DWR
Circuit [custom]8
Circuit [custom]8
Delay Time - Propagation150 ns
Independent Circuits1
Logic TypeD-Type Latch
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output Type1.81 mOhm
Package / Case20-SOIC
Package / Case [y]0.295 in
Package / Case [y]7.5 mm
Supplier Device Package20-SOIC
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 1.94
10$ 1.74
25$ 1.64
100$ 1.40
250$ 1.31
500$ 1.15
1000$ 0.95
Digi-Reel® 1$ 1.94
10$ 1.74
25$ 1.64
100$ 1.40
250$ 1.31
500$ 1.15
1000$ 0.95
Tape & Reel (TR) 2000$ 0.89
6000$ 0.85
10000$ 0.82
Texas InstrumentsLARGE T&R 1$ 1.55
100$ 1.28
250$ 0.92
1000$ 0.69

Description

General part information

TPIC6B273 Series

The TPIC6B273 is a monolithic, high-voltage, medium-current, power logic octal D-type latch with DMOS-transistor outputs designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads.

The TPIC6B273 contains eight positive-edge-triggered D-type flip-flops with a direct clear input. Each flip-flop features an open-drain power DMOS-transistor output.

When clear (CLR\) is high, information at the D inputs meeting the setup time requirements is transferred to the DRAIN outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input (CLK) is at either the high or low level, the D input signal has no effect at the output. An asynchronous CLR\ is provided to turn all eight DMOS-transistor outputs off. When data is low for a given output, the DMOS-transistor output is off. When data is high, the DMOS-transistor output has sink-current capability.

Documents

Technical documentation and resources