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Technical Specifications
Parameters and characteristics for this part
| Specification | CDC509PWRG4 |
|---|---|
| Differential - Input:Output | False |
| Divider/Multiplier | False |
| Frequency - Max [Max] | 125 MHz |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output | LVTTL |
| Package / Case | 24-TSSOP |
| Package / Case | 0.173 in, 4.4 mm |
| PLL | Yes with Bypass |
| Ratio - Input:Output | 1:9 |
| Supplier Device Package | 24-TSSOP |
| Type | PLL Clock Driver |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2000 | $ 11.50 | |
Description
General part information
CDC509 Series
The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCCand is designed to drive up to five clock loads per output.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Documents
Technical documentation and resources
No documents available