Specification	SN74LVC1G139DCTT

Circuit	1 x 2:4
Current - Output High, Low [x]	32 mA
Current - Output High, Low [y]	32 mA
Independent Circuits	1
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Supplier Device Package	SM8
Type	Decoder/Demultiplexer
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.65 V
Voltage Supply Source	Single Supply

SN74LVC1G139 Series

2-Line-to-4-Line Decoder

Part	Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Circuit	Mounting Type	Current - Output High, Low [y]	Current - Output High, Low [x]	Supplier Device Package	Operating Temperature [Max]	Operating Temperature [Min]	Independent Circuits	Voltage Supply Source	Package / Case [y]	Package / Case	Package / Case [y]
Texas Instruments 74LVC1G139DCTRE4	Decoder/Demultiplexer	5.5 V	1.65 V	1 x 2:4	Surface Mount	32 mA	32 mA	SM8	85 °C	-40 °C	1	Single Supply
Texas Instruments 74LVC1G139DCURG4	Decoder/Demultiplexer	5.5 V	1.65 V	1 x 2:4	Surface Mount	32 mA	32 mA		85 °C	-40 °C	1	Single Supply	2.3 mm	8-VFSOP	0.091 in
Texas Instruments SN74LVC1G139DCTR	Decoder/Demultiplexer	5.5 V	1.65 V	1 x 2:4	Surface Mount	32 mA	32 mA	SM8	85 °C	-40 °C	1	Single Supply
Texas Instruments 74LVC1G139DCURE4	Decoder/Demultiplexer	5.5 V	1.65 V	1 x 2:4	Surface Mount	32 mA	32 mA		85 °C	-40 °C	1	Single Supply	2.3 mm	8-VFSOP	0.091 in
Texas Instruments SN74LVC1G139DCTT	Decoder/Demultiplexer	5.5 V	1.65 V	1 x 2:4	Surface Mount	32 mA	32 mA	SM8	85 °C	-40 °C	1	Single Supply

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 1.32
		10	$ 1.18
		25	$ 1.12
		100	$ 0.92
	Digi-Reel®	1	$ 1.32
		10	$ 1.18
		25	$ 1.12
		100	$ 0.92
	Tape & Reel (TR)	250	$ 0.86
		500	$ 0.76
		1250	$ 0.60
		2500	$ 0.56
		6250	$ 0.53
		12500	$ 0.51
Texas Instruments	SMALL T&R	1	$ 1.13
		100	$ 0.77
		250	$ 0.59
		1000	$ 0.40

Description

General part information

SN74LVC1G139 Series

This SN74LVC1G139 2-to-4 line decoder is designed for 1.65-V to 5.5-V VCCoperation.

The SN74LVC1G139 2-line to 4-line decoder is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When used with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

NanoStar and NanoFree package technology is a major breakthrough in device packaging concepts, using the die as the package.

Documents

Technical documentation and resources

SN74LVC1G139DCTT

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SN74LVC1G139DCTT

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Technical Specifications

SN74LVC1G139 Series

Pricing

Description

SN74LVC1G139 Series

Documents

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

LOGIC Pocket Data Book (Rev. B)

LVC Characterization Information

Little Logic Guide 2018 (Rev. G)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Design Summary for WCSP Little Logic (Rev. B)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Live Insertion

Understanding Advanced Bus-Interface Products Design Guide

Texas Instruments Little Logic Application Report

Logic Guide (Rev. AB)

How to Select Little Logic (Rev. A)

Standard Linear & Logic for PCs, Servers & Motherboards

Low-Voltage Logic (LVC) Designer's Guide

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

SN74LVC1G139 2-to-4 Line Decoder datasheet (Rev. E)

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Signal Switch Data Book (Rev. A)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

CMOS Power Consumption and CPD Calculation (Rev. B)

Input and Output Characteristics of Digital Integrated Circuits

Selecting the Right Level Translation Solution (Rev. A)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Implications of Slow or Floating CMOS Inputs (Rev. E)

SN74LVC1G139 Series