SN74ALS164AD
Obsolete8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
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SN74ALS164AD
Obsolete8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALS164AD |
|---|---|
| Function | Serial to Parallel |
| Logic Type | Shift Register |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Push-Pull |
| Package / Case | 14-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 2.94 | |
| 10 | $ 2.64 | |||
| 50 | $ 2.50 | |||
| 100 | $ 2.17 | |||
| Texas Instruments | TUBE | 1 | $ 2.22 | |
| 100 | $ 1.95 | |||
| 250 | $ 1.36 | |||
| 1000 | $ 1.10 | |||
Description
General part information
SN74ALS164A Series
This 8-bit parallel-out serial shift register features AND-gated serial (A and B) inputs and an asynchronous clear (CLR\) input. The gated serial inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.
The SN74ALS164A is characterized for operation from 0°C to 70°C.
This 8-bit parallel-out serial shift register features AND-gated serial (A and B) inputs and an asynchronous clear (CLR\) input. The gated serial inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.
Documents
Technical documentation and resources
