Specification	CDC337DW

Differential - Input:Output	False
Frequency - Max [Max]	80 MHz
Input	TTL
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	CMOS
Package / Case	20-SOIC
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Ratio - Input:Output	1:8
Supplier Device Package	20-SOIC
Type	Fanout Buffer (Distribution)
Voltage - Supply [Max]	5.25 V
Voltage - Supply [Min]	4.75 V

CDC337 Series

Part	Type	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case [y]	Package / Case [y]	Frequency - Max [Max]	Number of Circuits	Supplier Device Package	Mounting Type	Input	Ratio - Input:Output	Output	Voltage - Supply [Min]	Voltage - Supply [Max]
Texas Instruments CDC337DWR	Fanout Buffer (Distribution)	85 °C	-40 °C	20-SOIC	0.295 in	7.5 mm	80 MHz	1	20-SOIC	Surface Mount	TTL	1:8	CMOS	4.75 V	5.25 V
Texas Instruments CDC337DW	Fanout Buffer (Distribution)	85 °C	-40 °C	20-SOIC	0.295 in	7.5 mm	80 MHz	1	20-SOIC	Surface Mount	TTL	1:8	CMOS	4.75 V	5.25 V
Texas Instruments CDC337DWG4	Fanout Buffer (Distribution)	85 °C	-40 °C	20-SOIC	0.295 in	7.5 mm	80 MHz	1	20-SOIC	Surface Mount	TTL	1:8	CMOS	4.75 V	5.25 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	75	$ 13.26
Texas Instruments	TUBE	1	$ 11.78
		100	$ 10.29
		250	$ 7.94
		1000	$ 7.10

Description

General part information

CDC337 Series

The CDC337 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the clock frequency and one-half the clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.

When the output-enable (OE\) input is low and the clear (CLR\) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions at CLK. Taking CLR\ low asynchronously resets the Q outputs to the low level. When OE\ is high, the outputs are in the high-impedance state.

The CDC337 is characterized for operation from -40°C to 85°C.

Documents

Technical documentation and resources

Clock Driver With 3-State Outputs datasheet (Rev. B)

Data sheet