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Technical Specifications
Parameters and characteristics for this part
| Specification | CD4075BM96 |
|---|---|
| Current - Output High, Low [custom] | 3.4 mA |
| Current - Output High, Low [custom] | 3.4 mA |
| Current - Quiescent (Max) [Max] | 1 çA |
| Input Logic Level - High [Max] | 11 V |
| Input Logic Level - High [Min] | 3.5 V |
| Input Logic Level - Low [Max] | 4 V |
| Input Logic Level - Low [Min] | 1.5 V |
| Logic Type | OR Gate |
| Max Propagation Delay @ V, Max CL | 90 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 3 |
| Number of Inputs | 3 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 14-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.47 | |
| 10 | $ 0.40 | |||
| 25 | $ 0.37 | |||
| 100 | $ 0.30 | |||
| 250 | $ 0.28 | |||
| 500 | $ 0.23 | |||
| 1000 | $ 0.18 | |||
| Digi-Reel® | 1 | $ 0.47 | ||
| 10 | $ 0.40 | |||
| 25 | $ 0.37 | |||
| 100 | $ 0.30 | |||
| 250 | $ 0.28 | |||
| 500 | $ 0.23 | |||
| 1000 | $ 0.18 | |||
| Tape & Reel (TR) | 2500 | $ 0.17 | ||
| 5000 | $ 0.15 | |||
| 12500 | $ 0.14 | |||
| 25000 | $ 0.14 | |||
| 62500 | $ 0.13 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.27 | |
| 100 | $ 0.21 | |||
| 250 | $ 0.15 | |||
| 1000 | $ 0.11 | |||
Description
General part information
CD4075B Series
CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.
The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.
Documents
Technical documentation and resources
