Specification	SN74AC74PWRG4

Clock Frequency	160 MHz
Current - Output High, Low	24 mA
Current - Quiescent (Iq)	2 µA
Function	Reset, Set(Preset)
Input Capacitance	3 pF
Max Propagation Delay @ V, Max CL	10 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	14-TSSOP
Package / Case [custom]	0.173 "
Package / Case [custom]	4.4 mm
Supplier Device Package	14-TSSOP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

SN74AC74-EP Series

Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset

Part	Package / Case [x]	Package / Case	Package / Case [y]	Max Propagation Delay @ V, Max CL	Current - Quiescent (Iq)	Clock Frequency	Supplier Device Package	Input Capacitance	Operating Temperature [Max]	Operating Temperature [Min]	Function	Voltage - Supply [Min]	Voltage - Supply [Max]	Trigger Type	Mounting Type	Number of Bits per Element	Current - Output High, Low	Type	Output Type	Number of Elements	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case [custom]	Package / Case [custom]
Texas Instruments SN74AC74NSR	0.209 "	14-SOIC	5.3 mm	10 ns	2 µA	160 MHz	14-SO	3 pF	85 °C	-40 °C	Reset Set(Preset)	2 V	6 V	Positive Edge	Surface Mount	1	24 mA	D-Type	Complementary	2
Texas Instruments CD74AC74M96E4	0.154 in	14-SOIC	3.9 mm	10 ns	4 çA	110 MHz		10 pF			Reset Set(Preset)	1.5 V	5.5 V	Positive Edge	Surface Mount	1	24 mA	D-Type	Complementary	2	125 °C	-55 °C
Texas Instruments SN74AC74DE4	0.154 in	14-SOIC	3.9 mm	10 ns	2 µA	160 MHz		3 pF	85 °C	-40 °C	Reset Set(Preset)	2 V	6 V	Positive Edge	Surface Mount	1	24 mA	D-Type	Complementary	2
Texas Instruments SN74AC74PWRE4		14-TSSOP		10 ns	2 µA	160 MHz	14-TSSOP	3 pF	85 °C	-40 °C	Reset Set(Preset)	2 V	6 V	Positive Edge	Surface Mount	1	24 mA	D-Type	Complementary	2			0.173 "	4.4 mm
Texas Instruments CD74AC74M	0.154 in	14-SOIC	3.9 mm	10 ns	4 çA	110 MHz		10 pF			Reset Set(Preset)	1.5 V	5.5 V	Positive Edge	Surface Mount	1	24 mA	D-Type	Complementary	2	125 °C	-55 °C
Texas Instruments CD74AC74M96G4	0.154 in	14-SOIC	3.9 mm	10 ns	4 çA	110 MHz		10 pF			Reset Set(Preset)	1.5 V	5.5 V	Positive Edge	Surface Mount	1	24 mA	D-Type	Complementary	2	125 °C	-55 °C
Texas Instruments SN74AC74D	0.154 in	14-SOIC	3.9 mm	6 ns	2 µA	160 MHz		3 pF	85 °C	-40 °C	Reset Set(Preset)	2 V	6 V	Positive Edge	Surface Mount	1	24 mA	D-Type	Complementary	2
Texas Instruments SN74AC74DR	0.154 in	14-SOIC	3.9 mm	6 ns	2 µA	160 MHz		3 pF	85 °C	-40 °C	Reset Set(Preset)	2 V	6 V	Positive Edge	Surface Mount	1	24 mA	D-Type	Complementary	2
Texas Instruments SN74AC74PWRG4		14-TSSOP		10 ns	2 µA	160 MHz	14-TSSOP	3 pF	85 °C	-40 °C	Reset Set(Preset)	2 V	6 V	Positive Edge	Surface Mount	1	24 mA	D-Type	Complementary	2			0.173 "	4.4 mm
Texas Instruments SN74AC74NG4	0.3 "	14-DIP	7.62 mm	10 ns	2 µA	160 MHz		3 pF	85 °C	-40 °C	Reset Set(Preset)	2 V	6 V	Positive Edge	Through Hole	1	24 mA	D-Type	Complementary	2

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Texas Instruments	LARGE T&R	1	$ 0.81
		100	$ 0.55
		250	$ 0.42
		1000	$ 0.28

Description

General part information

SN74AC74-EP Series

The SN74AC74 is a dual positive-edge-triggered D-type flip-flop.

A low level at the preset (PRE)\ or clear (CLR)\ input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

The SN74AC74 is a dual positive-edge-triggered D-type flip-flop.

Documents

Technical documentation and resources

SNx4AC74 Dual Positive-Edge-Triggered D-type Flip-Flops with Clear and Preset datasheet (Rev. G)

Data sheet

Power-Up Behavior of Clocked Devices (Rev. B)

Application note

CMOS Power Consumption and CPD Calculation (Rev. B)

Application note

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Application note

Live Insertion

Application note

SN74AC74PWRG4

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SN74AC74PWRG4

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Technical Specifications

SN74AC74-EP Series

Pricing

Description

SN74AC74-EP Series

Documents

Designing With Logic (Rev. C)

Input and Output Characteristics of Digital Integrated Circuits

HiRel Unitrode Power Management Brochure

Implications of Slow or Floating CMOS Inputs (Rev. E)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

TI IBIS File Creation, Validation, and Distribution Processes

LOGIC Pocket Data Book (Rev. B)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Logic Guide (Rev. AB)

SNx4AC74 Dual Positive-Edge-Triggered D-type Flip-Flops with Clear and Preset datasheet (Rev. G)

Power-Up Behavior of Clocked Devices (Rev. B)

CMOS Power Consumption and CPD Calculation (Rev. B)

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Live Insertion