
ADSP-BF561SKBZ600
ObsoleteBLACKFIN SYMMETRIC MULTI-PROCESSOR FOR CONSUMER MULTIMEDIA
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ADSP-BF561SKBZ600
ObsoleteBLACKFIN SYMMETRIC MULTI-PROCESSOR FOR CONSUMER MULTIMEDIA
Technical Specifications
Parameters and characteristics for this part
| Specification | ADSP-BF561SKBZ600 |
|---|---|
| Clock Rate (Frequency) | 600 MHz |
| Interface | UART, SPI, SSP |
| Mounting Type | Surface Mount |
| Non-Volatile Memory Type | External |
| On-Chip RAM | 328 kB |
| Operating Temperature (Max) | 70 °C |
| Operating Temperature (Min) | 0 °C |
| Package / Case | 297-BGA |
| Package Length | 27 mm |
| Package Name | 297-PBGA |
| Package Width | 27 mm |
| Type | Fixed Point |
| Voltage - Core | 1.35 V |
| Voltage - I/O (Option 1) | 2.5 V |
| Voltage - I/O (Option 2) | 3.3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | Updated |
|---|---|---|---|---|
CAD
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Description
General part information
ADSP-BF561 Series
The Blackfin®Processor family expands the performance envelope with the ADSP-BF561. With two high performance Blackfin Processor cores, flexible cache architecture, enhanced DMA subsystem, and Dynamic Power Management (DPM) functionality, the ADSP-BF561 can support complex control and signal processing tasks while maintaining extremely high data throughput.The ADSP-BF561 is a functional extension of the popular Blackfin Processor family and is ideally suited for a broad range of industrial, instrumentation, medical, and consumer appliance applications—allowing for scalability based upon the required data bandwidth and mix of control, plus signal processing needed in the end product.High-Level of Integration328 KBytes of on-chip memory configured as:32 KBytes of L1 instruction memory SRAM/Cache per core64 KBytes of L1 data memory SRAM/Cache per core4 KBytes of L1 scratchpad memory per core128 KBytes of low-latency shared L2 memory32-bit Memory Controller providing glueless connection to multiple banks of SDRAM, SRAM, Flash or ROM.Two Parallel Peripheral Interfaces Units supporting ITU-R 656 video data formats.Two dual-channel, full-duplex, synchronous serial ports supporting eight stereo I2S channels.Dual 16 Channel DMA Controllers, supporting one and two-dimension transfers.SPI-compatible Port.UART with support for IrDA®.12 timer/counters supporting PWM, pulsewidth and event count modes.48 Programmable Flags/General Purpose I/O.Event Handler.Dual Watchdog timers.PLL capable of 1x to 63x frequency multiplication.256-ball Mini-BGA and 297-ball Sparse PBGA packages.
Documents
Technical documentation and resources