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Technical Specifications
Parameters and characteristics for this part
| Specification | RM48L952DZWTT |
|---|---|
| Connectivity | I2C, SPI, LINbus, USB, MibSPI, CANbus, EBI/EMI, SCI, Ethernet, UART/USART |
| Core Processor | ARM« Cortex«-R4F |
| Core Size [Max] | 32 Bit |
| Core Size [Min] | 16 Bit |
| Data Converters [custom] | 12 |
| Data Converters [custom] | 24 |
| EEPROM Size | 64 K |
| Mounting Type | Surface Mount |
| Number of I/O | 120 |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | External |
| Package / Case | 337-LFBGA |
| Peripherals | WDT, DMA, PWM, POR |
| Program Memory Size | 3 MB |
| Program Memory Type | FLASH |
| RAM Size | 256 K |
| Speed | 220 MHz |
| Supplier Device Package | 337-NFBGA (16x16) |
| Voltage - Supply (Vcc/Vdd) [Max] | 1.32 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.14 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 43.26 | |
| 10 | $ 40.36 | |||
| 25 | $ 38.67 | |||
| 90 | $ 35.04 | |||
| 270 | $ 33.83 | |||
| Texas Instruments | JEDEC TRAY (10+1) | 1 | $ 36.61 | |
| 100 | $ 32.54 | |||
| 250 | $ 26.75 | |||
| 1000 | $ 23.93 | |||
Description
General part information
RM48L952 Series
The RM48L952 device is a high-performance microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.
The RM48L952 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and has configurations that can run up to 220 MHz, providing up to 365 DMIPS. The device supports the little-endian [LE] format.
The RM48L952 device has 3MB of integrated flash and 256KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 220 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes.
Documents
Technical documentation and resources
