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Technical Specifications
Parameters and characteristics for this part
| Specification | SMV512K32HFG |
|---|---|
| Access Time | 20 ns |
| Memory Format | SRAM |
| Memory Interface | Parallel |
| Memory Organization | 512 K |
| Memory Size | 16 Mb |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 76-CBQFP Bumpered |
| Supplier Device Package | 76-CFP (45.72x51.31) |
| Technology | SRAM |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.7 V |
| Write Cycle Time - Word, Page | 20 ns |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | JEDEC TRAY (5+1) | 1 | $ 7242.30 | |
| 10 | $ 6854.31 | |||
| 100 | $ 6466.34 | |||
Description
General part information
SMV512K32-SP Series
The SMV512K32 is a high performance asynchronous CMOS SRAM organized as 524,288 words by 32 bits. It is pin selectable between two modes: master or slave. The master device selection provides user defined autonomous EDAC scrubbing options. The slave device selection employs a scrub on demand feature that can be initiated by a master device. Three read cycles and four write cycles (described below) are available depending on the user needs.
The SMV512K32 is a high performance asynchronous CMOS SRAM organized as 524,288 words by 32 bits. It is pin selectable between two modes: master or slave. The master device selection provides user defined autonomous EDAC scrubbing options. The slave device selection employs a scrub on demand feature that can be initiated by a master device. Three read cycles and four write cycles (described below) are available depending on the user needs.
Documents
Technical documentation and resources