Specification	SN74LVTH241DW

Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Logic Type	Buffer, Non-Inverting
Mounting Type	Surface Mount
Number of Bits per Element	4
Number of Elements	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	3-State
Package / Case	20-SOIC
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Supplier Device Package	20-SOIC
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2.7 V

SN74LVTH241 Series

8-ch, 2.7-V to 3.6-V buffers with bus-hold, TTL-compatible CMOS inputs and 3-state outputs

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Elements	Operating Temperature [Max]	Operating Temperature [Min]	Number of Bits per Element	Supplier Device Package	Output Type	Mounting Type	Package / Case	Package / Case	Package / Case	Logic Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case [y]	Package / Case [y]	Package / Case [x]
Texas Instruments SN74LVTH241NSR	64 mA	32 mA	2	85 °C	-40 °C	4	20-SO	3-State	Surface Mount	20-SOIC	0.209 "	5.3 mm	Buffer Non-Inverting	2.7 V	3.6 V
Texas Instruments SN74LVTH241DBR	64 mA	32 mA	2	85 °C	-40 °C	4	20-SSOP	3-State	Surface Mount	20-SSOP			Buffer Non-Inverting	2.7 V	3.6 V
Texas Instruments SN74LVTH241DW	64 mA	32 mA	2	85 °C	-40 °C	4	20-SOIC	3-State	Surface Mount	20-SOIC			Buffer Non-Inverting	2.7 V	3.6 V	0.295 in	7.5 mm
Texas Instruments SN74LVTH241PW	64 mA	32 mA	2	85 °C	-40 °C	4	20-TSSOP	3-State	Surface Mount	20-TSSOP			Buffer Non-Inverting	2.7 V	3.6 V	4.4 mm		0.173 in
Texas Instruments SN74LVTH241NSRE4	64 mA	32 mA	2	85 °C	-40 °C	4	20-SO	3-State	Surface Mount	20-SOIC	0.209 "	5.3 mm	Buffer Non-Inverting	2.7 V	3.6 V
Texas Instruments SN74LVTH241PWR	64 mA	32 mA	2	85 °C	-40 °C	4	20-TSSOP	3-State	Surface Mount	20-TSSOP			Buffer Non-Inverting	2.7 V	3.6 V	4.4 mm		0.173 in
Texas Instruments SN74LVTH241DWRG4	64 mA	32 mA	2	85 °C	-40 °C	4	20-SOIC	3-State	Surface Mount	20-SOIC			Buffer Non-Inverting	2.7 V	3.6 V	0.295 in	7.5 mm
Texas Instruments SN74LVTH241DWR	64 mA	32 mA	2	85 °C	-40 °C	4	20-SOIC	3-State	Surface Mount	20-SOIC			Buffer Non-Inverting	2.7 V	3.6 V	0.295 in	7.5 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 0.76
		10	$ 0.68
		25	$ 0.65
		100	$ 0.53
		250	$ 0.50
		500	$ 0.44
		1000	$ 0.41
Texas Instruments	TUBE	1	$ 0.81
		100	$ 0.62
		250	$ 0.46
		1000	$ 0.33

Description

General part information

SN74LVTH241 Series

These octal buffers/drivers are designed specifically for low-voltage (3.3-V) VCCoperation, with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH241 devices are organized as two 4-bit line drivers with separate output-enable (1OE\, 2OE) inputs. When 1OE\ is low or 2OE is high, the devices pass noninverted data from the A inputs to the Y outputs. When 1OE\ is high or 2OE is low, the outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

Documents

Technical documentation and resources

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Application note

LVT-to-LVTH Conversion

Application note

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Application note

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

TI IBIS File Creation, Validation, and Distribution Processes

Application note

LVT Family Characteristics (Rev. A)

Application note

SN74LVTH241DW

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SN74LVTH241DW

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Technical Specifications

SN74LVTH241 Series

Pricing

Description

SN74LVTH241 Series

Documents

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

LVT-to-LVTH Conversion

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

SN54LVTH241, SN74LVTH241 datasheet (Rev. K)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Live Insertion

Understanding Advanced Bus-Interface Products Design Guide

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Input and Output Characteristics of Digital Integrated Circuits

Advanced Bus Interface Logic Selection Guide

An Overview of Bus-Hold Circuit and the Applications (Rev. B)

LOGIC Pocket Data Book (Rev. B)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Logic Guide (Rev. AB)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

TI IBIS File Creation, Validation, and Distribution Processes

LVT Family Characteristics (Rev. A)

SN74LVTH241 Series