Integrated Circuits (ICs)

SN5476J

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Texas Instruments

DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR

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Integrated Circuits (ICs)

SN5476J

Active

Texas Instruments

DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR

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DocumentsDatasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN5476J

Clock Frequency	20 MHz
Function	Reset, Set(Preset)
Max Propagation Delay @ V, Max CL	40 ns
Mounting Type	Through Hole
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Complementary
Package / Case	7.62 mm, 0.3 in
Package / Case	16-CDIP
Supplier Device Package	16-CDIP
Trigger Type	Positive Edge
Type	JK Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN5476 Series

Dual J-K Flip-Flops With Preset And Clear

Part	Trigger Type	Package / Case	Package / Case	Function	Number of Elements	Number of Bits per Element	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Output Type	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Clock Frequency	Max Propagation Delay @ V, Max CL	Type
Texas Instruments SN5476J	Positive Edge	0.3 in 7.62 mm	16-CDIP	Reset Set(Preset)	2	1	4.5 V	5.5 V	16-CDIP	Complementary	Through Hole	125 °C	-55 °C	20 MHz	40 ns	JK Type

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Texas Instruments	TUBE	1	$ 15.08
		100	$ 13.17
		250	$ 10.16
		1000	$ 9.08

Description

General part information

SN5476 Series

The '76 contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs. The '76 is a positive-edge-triggered flip-flop. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS76A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. The preset and clear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the function table.

The SN5476 and the SN54LS76A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7476 and the SN74LS76A are characterized for operation from 0°C to 70°C.

Documents

Technical documentation and resources