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40-LFCSP-WQ
Integrated Circuits (ICs)

AD5348BCPZ

Active
Analog Devices Inc./Maxim Integrated

2.5 V TO 5.5 V, PARALLEL INTERFACE OCTAL VOLTAGE OUTPUT 12-BIT D/A CONVERTER

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40-LFCSP-WQ
Integrated Circuits (ICs)

AD5348BCPZ

Active
Analog Devices Inc./Maxim Integrated

2.5 V TO 5.5 V, PARALLEL INTERFACE OCTAL VOLTAGE OUTPUT 12-BIT D/A CONVERTER

Technical Specifications

Parameters and characteristics for this part

SpecificationAD5348BCPZ
ArchitectureString DAC
Data InterfaceParallel
Differential OutputNo
DNL (LSB) Tolerance0.2 LSB
INL (LSB) Tolerance2 LSB
Mounting TypeSurface Mount
Number of Bits12 bits
Number of D/A Converters8 count
Operating Temperature (Max)105 °C
Operating Temperature (Min)-40 °C
Output TypeVoltage - Buffered
Package / Case40-WFQFN Exposed Pad, CSP
Package Length6 mm
Package Name40-LFCSP-WQ
Package Width6 mm
Reference TypeExternal
Settling Time10 µs
Voltage - Supply, Analog (Max)5.5 V
Voltage - Supply, Analog (Min)2.5 V
Voltage - Supply, Digital (Max)5.5 V
Voltage - Supply, Digital (Min)2.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$Updated
DigikeyTray 1$ 31.20<1d
10$ 25.25
33$ 23.38
132$ 21.87
264$ 21.31

CAD

3D models and CAD resources for this part

Description

General part information

AD5348 Series

TheAD5346/AD5347/ AD5348 are octal 8-, 10-, and 12- bit DACs, operating from a 2.5 V to 5.5 V supply. These devices incorporate an on-chip output buffer that can drive the output to both supply rails, and also allows a choice of buffered or unbuffered reference input.The AD5346 / AD5347 / AD5348 have a parallel interface.CSselects the device and data is loaded into the input registers on the rising edge of WR. A readback feature allows the internal DAC registers to be read back through the digital port.The GAIN pin on these devices allows the output range to be set at 0 V to VREFor 0 V to 2 x VREF.Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin.An asynchronous CLR input is also provided, which resets the contents of the Input Register and the DAC Register to all zeros. These devices also incorporate a power-on-reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device. All three parts are pin-compatible, which allows the user to select the amount of resolution appropriate for their application without redesigning their circuit board.APPLICATIONSPortable battery-powered instrumentsDigital gain and offset adjustmentProgrammable voltage and current sourcesOptical networkingAutomatic test equipmentMobile communicationsProgrammable attenuatorsIndustrial process control