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108-CSPBGA
Integrated Circuits (ICs)

AD5378ABC

Obsolete
Analog Devices Inc./Maxim Integrated

IC DAC 14BIT V-OUT 108CSPBGA

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108-CSPBGA
Integrated Circuits (ICs)

AD5378ABC

Obsolete
Analog Devices Inc./Maxim Integrated

IC DAC 14BIT V-OUT 108CSPBGA

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationAD5378ABC
ArchitectureString DAC
Data InterfaceDSP, SPI
Differential OutputNo
DNL (Max) (LSB)1.5 LSB
DNL Maximum (LSB)1.5 LSB
DNL Minimum (LSB)-1 LSB
INL (Max) (LSB)3 LSB
INL (Max) (LSB) Tolerance3 LSB
Mounting TypeSurface Mount
Number of Bits14 bits
Number of D/A Converters32 count
Operating Temperature (Max)85 °C
Operating Temperature (Min)-40 °C
Output TypeVoltage - Buffered
Package / CaseCSPBGA, 108-BGA
Package Length13 mm
Package Name108-CSPBGA
Package Width13 mm
Reference TypeExternal
Settling Time30 µs
Voltage - Supply, Analog (Range 1 Max)16.5 V
Voltage - Supply, Analog (Range 1 Min)8.5 V
Voltage - Supply, Analog (Range 2 Max)16.5 V
Voltage - Supply, Analog (Range 2 Min)-3 V
Voltage - Supply, Digital (Max)5.5 V
Voltage - Supply, Digital (Min)2.7 V

Pricing

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Description

General part information

AD5378 Series

The AD5378 contains 32 14-bit DACs in one CSPBGA package. The AD5378 provides a bipolar output range determined by the voltages applied to the VREF(+) and VREF(−) inputs. The maximum output voltage span is 17.5 V, corresponding to a bipolar output range of −8.75 V to +8.75 V, and is achieved with reference voltages of VREF(−) = −3.5 V and VREF(+) = +5 V.The AD5378 guarantees operation over a wide VSS/VDDsupply range from ±11.4 V to ±16.5 V. The output amplifier headroom requirement is 2.5 V operating with a load current of 1.5 mA, and 2 V operating with a load current of 0.5 mA.The AD5378 contains a double-buffered parallel interface in which 14 data bits are loaded into one of the input registers under the control of theWR,CS, and DAC channel address pins, A0 to A7. It also has a 3-wire serial interface, which is compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.The DAC outputs are updated when the DAC registers receive new data. All the outputs can be updated simultaneously by taking theLDACinput low. Each channel has a programmable gain and an offset adjust register.Each DAC output is gained and buffered on-chip with respect to an external REFGND input. The DAC outputs can also be switched to REFGND via theCLRpin. Table 1 and Table 2 show the product portfolio for high channel count bipolar and unipolar voltage output DACs.APPLICATIONSLevel setting in automatic test equipment (ATE)Variable optical attenuators (VOAs)Optical switchesIndustrial control systems

Documents

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