ADS8365IPAG
Active16-BIT 250KSPS 6-CH SIMULTANEOUS SAMPLING SAR ADC
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ADS8365IPAG
Active16-BIT 250KSPS 6-CH SIMULTANEOUS SAMPLING SAR ADC
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Technical Specifications
Parameters and characteristics for this part
| Specification | ADS8365IPAG |
|---|---|
| Architecture | SAR |
| Configuration | S/H-ADC |
| Data Interface | Parallel |
| Features | Simultaneous Sampling, Selectable Address |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 6 |
| Number of Bits | 16 |
| Number of Inputs | 6 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 64-TQFP |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | External, Internal |
| Sampling Rate (Per Second) | 250 k |
| Supplier Device Package | 64-TQFP (10x10) |
| Voltage - Supply, Analog | 5 V |
| Voltage - Supply, Digital | 5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 34.56 | |
| 10 | $ 31.88 | |||
| 25 | $ 30.44 | |||
| 160 | $ 27.22 | |||
| 320 | $ 25.97 | |||
| Texas Instruments | JEDEC TRAY (10+1) | 1 | $ 30.74 | |
| 100 | $ 27.32 | |||
| 250 | $ 22.46 | |||
| 1000 | $ 20.09 | |||
Description
General part information
ADS8365 Series
The ADS8365 includes six, 16-bit, 250kSPS analog-to-digital converters (ADCs) with six fully differential input channels grouped into three pairs for high-speed simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the ADC. This architecture provides excellent common-mode rejection of 80dB at 50kHz, which is important in high-noise environments.
The ADS8365 offers a flexible, high-speed parallel interface with a direct address mode, a cycle, and a FIFO mode. The output data for each channel is available as a 16-bit word.
The ADS8365 includes six, 16-bit, 250kSPS analog-to-digital converters (ADCs) with six fully differential input channels grouped into three pairs for high-speed simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the ADC. This architecture provides excellent common-mode rejection of 80dB at 50kHz, which is important in high-noise environments.
Documents
Technical documentation and resources
