
LMK04832NKDT
ActiveULTRA-LOW-NOISE, 3.2-GHZ, 15-OUTPUT, JESD204B CLOCK JITTER CLEANER WITH DUAL LOOP
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LMK04832NKDT
ActiveULTRA-LOW-NOISE, 3.2-GHZ, 15-OUTPUT, JESD204B CLOCK JITTER CLEANER WITH DUAL LOOP
Technical Specifications
Parameters and characteristics for this part
| Specification | LMK04832NKDT |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Divider/Multiplier | Yes/No |
| Frequency - Max [Max] | 3.255 GHz |
| Input | Clock |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | CML, HSDS, LVPECL, LVCMOS, LCPECL, LVDS |
| Package / Case | 64-WFQFN Exposed Pad |
| PLL | True |
| Ratio - Input:Output | 3:14 |
| Supplier Device Package | 64-WQFN (9x9) |
| Type | Jitter Cleaner |
| Voltage - Supply [Max] | 3.45 V |
| Voltage - Supply [Min] | 3.15 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 36.37 | |
| 10 | $ 33.54 | |||
| 25 | $ 32.03 | |||
| 100 | $ 28.64 | |||
| Digi-Reel® | 1 | $ 36.37 | ||
| 10 | $ 33.54 | |||
| 25 | $ 32.03 | |||
| 100 | $ 28.64 | |||
| Tape & Reel (TR) | 250 | $ 27.32 | ||
| Texas Instruments | SMALL T&R | 1 | $ 30.97 | |
| 100 | $ 27.05 | |||
| 250 | $ 20.86 | |||
| 1000 | $ 18.66 | |||
Description
General part information
LMK04832 Series
The LMK04832 is an ultra-high performance clock conditioner with JEDEC JESD204B support and is also pin compatible with the LMK0482x family of devices.
The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems.
The LMK04832 can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.
Documents
Technical documentation and resources