74LV165D-Q100J
Active8-BIT PARALLEL-IN/SERIAL-OUT SHIFT REGISTER
Deep-Dive with AI
Search across all available documentation for this part.
74LV165D-Q100J
Active8-BIT PARALLEL-IN/SERIAL-OUT SHIFT REGISTER
Technical Specifications
Parameters and characteristics for this part
| Specification | 74LV165D-Q100J |
|---|---|
| Function | Parallel to Serial |
| Grade | Automotive |
| Logic Type | Shift Register |
| Mounting Type | Surface Mount |
| Number of Bits per Element [custom] | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 C |
| Output Type | Complementary |
| Package / Case | 16-SOIC |
| Package / Case | 0.154 in, 3.9 mm |
| Qualification | AEC-Q100 |
| Supplier Device Package | 16-SO |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 1 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 0.23 | |
Description
General part information
74LV165D-Q100 Series
The 74LV165-Q100 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 andQ7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. WhenPLis HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH onCEwill disable the CP input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.
Documents
Technical documentation and resources