74HCT174PW,118
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 1-ELEMENT 16-PIN TSSOP T/R
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74HCT174PW,118
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 1-ELEMENT 16-PIN TSSOP T/R
Technical Specifications
Parameters and characteristics for this part
| Specification | 74HCT174PW,118 |
|---|---|
| Clock Frequency [custom] | 69 MHz |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Output High, Low [custom] | 4 mA |
| Current - Quiescent (Iq) | 8 ÁA |
| Input Capacitance | 3.5 pF |
| Max Propagation Delay @ V, Max CL | 35 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element [custom] | 6 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Non-Inverted |
| Package / Case | 16-TSSOP |
| Package / Case [y] | 4.4 mm |
| Package / Case [y] | 0.173 in |
| Supplier Device Package | 16-TSSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 1890 | $ 0.65 | |
Description
General part information
74HCT174PW Series
The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW onMRcauses the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Documents
Technical documentation and resources