
CY7C10612G30-10ZSXI
ActiveSRAM CHIP ASYNC SINGLE 3.3V 16M-BIT 1M X 16 10NS 54-PIN TSOP-II TRAY
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CY7C10612G30-10ZSXI
ActiveSRAM CHIP ASYNC SINGLE 3.3V 16M-BIT 1M X 16 10NS 54-PIN TSOP-II TRAY
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Technical Specifications
Parameters and characteristics for this part
| Specification | CY7C10612G30-10ZSXI |
|---|---|
| Access Time | 10 ns |
| Memory Format | SRAM |
| Memory Interface | Parallel |
| Memory Organization | 1 M |
| Memory Size | 2 MB |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 C |
| Operating Temperature [Min] | -40 ¯C |
| Supplier Device Package | 54-TSOP II |
| Technology | SRAM - Asynchronous |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
| Write Cycle Time - Word, Page | 10 ns |
Pricing
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Description
General part information
CY7C10612 Series
CY7C10612G30-10ZSXI is a high performance CMOS fast static RAM device with embedded ECC. The device includes an error indication pin that signals an error detection and correction event during a read cycle. To write to the device, take chip enables (active-low CE) and write enable (active-low WE) input LOW. To read from the device, take chip enable (active-low CE) and output enable (active-low OE) LOW while forcing the write enable (active-low WE) HIGH. The input or output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (active-low CE HIGH), the outputs are disabled (active-low OE HIGH), the active-low BHE and active-low BLE are disabled (active-low BHE, active-low BLE HIGH), or during a write operation (active-low CE LOW and active-low WE LOW).
Documents
Technical documentation and resources