
LT8440RS8E#PBF
UnknownPOWER CONDITIONER FOR APL FIELD DEVICES
Deep-Dive with AI
Search across all available documentation for this part.

LT8440RS8E#PBF
UnknownPOWER CONDITIONER FOR APL FIELD DEVICES
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | LT8440RS8E#PBF |
|---|---|
| Applications | APL Field Devices |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 150 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | Exposed Pad, 8-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 8-SOIC-EP |
| Voltage - Supply [Max] | 36 V |
| Voltage - Supply [Min] | 6 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | Updated |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 0.00 | 1m+ |
Description
General part information
LT8440 Series
The LT8440 is a power conditioner for intrinsically safe, industrial ethernet ports in hazardous or explosive environments. The internal pass transistor is normally fully enhanced to deliver power to the load efficiently. In case of load circuit failures, the FET is modulated to limit the power to less than 650mW if line voltage ≤ 18.5V or less than 35mA if line voltage > 18.5V. The internal shunt transistor draws current parallel with the load up to the 500mW minimum guaranteed for Class A load power ports in compliance with Advanced Physical Layer (APL) standard or to 20mA minimum guaranteed if line voltage > 18.5V. The line voltage is sensed with two input pins that are insensitive to polarity, which can be connected in front of the port rectifier and incorporate the rectifier power consumption in the limitation of total power. The line current is measured as a voltage across the internal sense resistor, and the shunt current and the current limit are automatically adjusted for line voltage.The LT8440 is packaged in an 8-lead SOIC with pin spacing that satisfies the device under coating specification so that shorts from pin to pin are countable faults when the circuit is examined for intrinsic safety at the highest levels of protection.APPLICATIONSIndustrial EthernetAdvanced Physical LayerCurrent Limiting
Documents
Technical documentation and resources