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ADSP-21160MKBZ-80
Integrated Circuits (ICs)

ADSP-21160MKBZ-80

Active
Analog Devices Inc./Maxim Integrated

SHARC, 80 MHZ, 600 MFLOPS, 3.3 V I/O, 2.5 V CORE, FLOATING POINT

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ADSP-21160MKBZ-80
Integrated Circuits (ICs)

ADSP-21160MKBZ-80

Active
Analog Devices Inc./Maxim Integrated

SHARC, 80 MHZ, 600 MFLOPS, 3.3 V I/O, 2.5 V CORE, FLOATING POINT

Technical Specifications

Parameters and characteristics for this part

SpecificationADSP-21160MKBZ-80
Clock Rate (Frequency)80 MHz
InterfaceHost Interface, Serial Port, Link Port
Mounting TypeSurface Mount
Non-Volatile Memory TypeExternal
On-Chip RAM512 kB
Operating Temperature (Max)85 °C
Operating Temperature (Min)0 °C
Package / Case400-BBGA
Package Length27 mm
Package Name400-PBGA
Package Width27 mm
TypeFloating Point
Voltage - Core2.5 V
Voltage - I/O3.3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$Updated
DigikeyTray 1$ 406.36<1d
10$ 394.01

CAD

3D models and CAD resources for this part

Description

General part information

ADSP-21160M Series

The ADSP-21160M DSP is a SHARC processor that is optimized for applications such as telephony, medical imaging, radar/sonar electronics, communications, 3D graphics and imaging. The ADSP-21160M features a Single-Instruction-Multiple-Data (SIMD) architecture.Using two computational units (ALU, Barrel Shifter, MAC, Register files), the ADSP-21160M can have a five fold performance increase versus the ADSP-2106x on a range of DSP algorithms. It is code compatible with ADI's popular first generation ADSP-2106x SHARC DSPs. Like other SHARCs, the ADSP-21160M is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160M includes an 80 MHz core for processing both 32-bit fixed-point and (32-bit, 40-bit) floating-point data types, a dual-ported 4 Mbit on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal busses to eliminate I/O bottlenecks.The ADSP-21160M is optimized for multiprocessing topologies; SHARC supports multiprocessing via link ports or an external port. In the diagram below, both cluster and link port multiprocessing is shown. Over the external port up to six 21160Ms may be connected together without any additional support logic. The arbitration for this shared bus is integrated on-chip. Each SHARC in the cluster has access to every SHARC's internal memory. Through the external port connection, optional external memory may be shared as well.The six link ports are another way to gluelessly connect a multiprocessing system. Both, the links and the cluster can be used simultaneously and systems with hundreds of SHARC DSPs can be developed using both peripherals.Maximize Speed, Minimize SizeThe ADSP-21160M is offered in a 27mm x 27mm 400-ball PBGA (Plastic Ball Grid Array) package 40% smaller than processors in this performance class.More Processing Per WattIn addition to small size and high performance, the 21160M's power dissipation enables new levels of MFLOPS per watt. The ADSP-21160M typical power dissipation is 2 watts, enabling 240 MFLOPS of performance per watt. This allows designers to use multiple processors on a PCI card within the PCI power limit of 25 watts. With eight 21160M DSPs, providing 480 MFLOPS each, a standard PCI card design can obtain 3.84 GFLOPS performance and leave 9 watts for other circuitry.The ADSP-21160M is supported by hundreds of readily available third-party hardware and software products and ADI's powerful VisualDSP++ development system, allowing for fast and easy development, debug and deployment.

Documents

Technical documentation and resources

EE-68: Analog Devices JTAG Emulation Technical Reference (Rev.10)

Application Note

EE-106: Link Port Open Systems Interconnect Cable Standard

Application Note

EE-128: DSP in C++: Calling Assembly Class Member Functions From C++

Application Note

EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev.3)

Application Note

EE-284: Implementing Overlays on ADSP-21160 SHARC® Processors (Rev.1)

Application Note

EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev.14)

Application Note

Apex-ICE USB Emulator Hardware Installation Guide (Rev.6.0)

Legacy Emulator Manual

EE-110: A Quick Primer on ELF and DWARF File Formats

Application Note

EE-241: SHARC® DSPs to TigerSHARC® Processors Code Porting Guide (Rev.1)

Application Note

EE-323: Implementing Dynamically Loaded Software Modules (Rev.1)

Application Note

EE-195: Moving from the ADSP-21160M SHARC® DSP to the ADSP-21160N SHARC DSP

Application Note

EE-141: Benchmarking C Code on the ADSP-2106x and the ADSP-2116x Family of DSPs

Application Note

EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev.1)

Application Note

EE-340: Connecting SHARC®and Blackfin®Processors over SPI (Rev.1)

Application Note

EE-134: Writing C Compatible Assembly Code Interrupt Handlers for the SHARC® Family

Application Note

EE-305: Designing and Debugging Systems with SHARC Processors (Rev.1)

Application Note

EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs

Application Note

ADSP-21160M_SHARC_Anomaly_List_for_Revisions 0.0,0.1,1.1,1.2 (Rev.K)

Integrated Circuit Anomaly

ADSP-21160 SHARC®DSP Hardware Reference (Rev.4.1)

Processor Manual

EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev.1)

Application Note

EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev.2)

Application Note

EE-223: In-Circuit Flash Programming on SHARC® Processors (Rev.2)

Application Note

EE-253: Power Bypass Decoupling of SHARC® Processors (Rev.1)

Application Note

EE-160: Examining ADSP-21160 Link Port Backward Compatibility to the ADSP-2106x Link Ports

Application Note

EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev.1)

Application Note

EE-140: Using the ADSP-21160 Serial Ports in Multi-channel Mode

Application Note

EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev.3)

Application Note

EE-77: SHARC Link Port Booting

Application Note

Package Drawing - 400-Ball PBGA (27mm x 27mm)

Package Drawing

ADSP-21160 SHARC®DSP Instruction Set Reference (Rev.2.1)

Processor Manual

Summit-ICE PCI Emulator Hardware Installation Guide (Rev.4)

Legacy Emulator Manual

EE-104: Setting Up Streams with the VisualDSP Debugger

Application Note

SHARC Processor Family

Product Highlight

EE-332: Cycle Counting and Profiling (Rev.2)

Application Note

EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev.1)

Application Note

EE-132: Placing C Code and Data Modules in SHARC memory using VisualDSP++™

Application Note

EE-148: Introduction to SHARC® Multiprocessor Systems using VisualDSP++™

Application Note

ADSP-21160 EZ-KIT Lite®Evaluation System Manual (Rev.5.0)

User Guide

EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev.1)

Application Note

EE-177: SHARC® SPI Slave Booting (Rev.3)

Application Note

ADSP-21061, 21065L and the 21160M EZ-KIT Lite®Installation Procedure (Rev.3.1)

User Guide

ADSP-21160M/ADSP-21160N: SHARC Digital Signal Processor Data Sheet (Rev.D)

Data Sheet