Integrated Circuits (ICs)

MC14024BFR1

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ON Semiconductor

BINARY COUNTER

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Integrated Circuits (ICs)

MC14024BFR1

Active

ON Semiconductor

BINARY COUNTER

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Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	MC14024BFR1

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MC14024B Series

7-Stage Ripple Counter

Part	Reset	Logic Type	Count Rate	Voltage - Supply [Max]	Voltage - Supply [Min]	Mounting Type	Trigger Type	Number of Bits per Element	Operating Temperature [Min]	Operating Temperature [Max]	Package / Case [x]	Package / Case [y]	Package / Case	Direction	Number of Elements	Supplier Device Package
ON Semiconductor MC14024BD	Asynchronous	Binary Counter	12 MHz	18 V	3 V	Surface Mount	Negative Edge	7	-55 °C	125 °C	0.154 in	3.9 mm	14-SOIC	Up	1
ON Semiconductor NLV14024BDG	Asynchronous	Binary Counter	12 MHz	18 V	3 V	Surface Mount	Negative Edge	7	-55 °C	125 °C	0.154 in	3.9 mm	14-SOIC	Up	1
ON Semiconductor MC14024BFR1
ON Semiconductor MC14024BCPG	Asynchronous	Binary Counter	12 MHz	18 V	3 V	Through Hole	Negative Edge	7	-55 °C	125 °C	0.3 "	7.62 mm	14-DIP	Up	1
ON Semiconductor MC14024BFL2
ON Semiconductor MC14024BFELG	Asynchronous	Binary Counter	12 MHz	18 V	3 V	Surface Mount	Negative Edge	7	-55 °C	125 °C	0.209 "	5.3 mm	14-SOIC	Up	1	SOEIAJ-14
ON Semiconductor MC14024BDG	Asynchronous	Binary Counter	12 MHz	18 V	3 V	Surface Mount	Negative Edge	7	-55 °C	125 °C	0.154 in	3.9 mm	14-SOIC	Up	1
ON Semiconductor MC14024BDR2G	Asynchronous	Binary Counter	12 MHz	18 V	3 V	Surface Mount	Negative Edge	7	-55 °C	125 °C	0.154 in	3.9 mm	14-SOIC	Up	1

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Bulk	2959	$ 0.10

Description

General part information

MC14024B Series

The MC14024B is a 7-stage ripple counter with short propagation delays and high maximum clock rates. The Reset input has standard noise immunity, however the Clock input has increased noise immunity due to Hysteresis. The output of each counter stage is buffered.

Documents

Technical documentation and resources

No documents available