SN74AVC16834DGVR
Active18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
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SN74AVC16834DGVR
Active18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AVC16834DGVR |
|---|---|
| Current - Output High, Low [custom] | 12 mA |
| Current - Output High, Low [custom] | 12 mA |
| Logic Type | Universal Bus Driver |
| Mounting Type | Surface Mount |
| Number of Circuits | 18-Bit |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 C |
| Package / Case | 0.173 ", 4.4 mm |
| Package / Case | 56-TFSOP |
| Supplier Device Package | 56-TVSOP |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.4 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 2.02 | |
| Digi-Reel® | 1 | $ 2.02 | ||
| N/A | 0 | $ 1.09 | ||
| Tape & Reel (TR) | 2000 | $ 0.92 | ||
| 6000 | $ 0.89 | |||
| 10000 | $ 0.85 | |||
| Texas Instruments | LARGE T&R | 1 | $ 1.37 | |
| 100 | $ 1.20 | |||
| 250 | $ 0.84 | |||
| 1000 | $ 0.68 | |||
Description
General part information
74AVC16834 Series
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOLvs IOLand VOHvs IOHcurves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,AVC Logic Family Technology and Applications, literature number SCEA006, andDynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.
This 18-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
Documents
Technical documentation and resources