Integrated Circuits (ICs)
9DB102BFLF
ObsoleteRenesas Electronics Corporation
2-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN2
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Documents9DB102 Datasheet
Integrated Circuits (ICs)
9DB102BFLF
ObsoleteRenesas Electronics Corporation
2-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN2
Deep-Dive with AI
Documents9DB102 Datasheet
Technical Specifications
Parameters and characteristics for this part
| Specification | 9DB102BFLF |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 101 MHz |
| Input | Clock |
| Main Purpose | PCI Express (PCIe) |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output | HCSL |
| Package / Case | 20-SSOP |
| Package / Case [custom] | 0.154 in |
| Package / Case [custom] | 3.9 mm |
| PLL | True |
| Ratio - Input:Output [custom] | 1:2 |
| Supplier Device Package | 20-QSOP |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Bulk | 1000 | $ 0.89 | |
Description
General part information
9DB102 Series
The 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.
Documents
Technical documentation and resources