
MAXQ1850-BNS+T
UnknownDEEPCOVER SECURE MICROCONTROLLER WITH RAPID ZEROIZATION TECHNOLOGY AND CRYPTOGRAPHY
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MAXQ1850-BNS+T
UnknownDEEPCOVER SECURE MICROCONTROLLER WITH RAPID ZEROIZATION TECHNOLOGY AND CRYPTOGRAPHY
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Technical Specifications
Parameters and characteristics for this part
| Specification | MAXQ1850-BNS+T |
|---|---|
| Applications | Security |
| Controller Series | MAXQ™ |
| Core Processor | MAXQ |
| Interface | USB, UART/USART, SPI |
| Mounting Type | Surface Mount |
| Number of I/O | 16 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 C |
| Package / Case | 40-WFQFN Exposed Pad |
| Program Memory Type | 256 kB |
| Program Memory Type | FLASH |
| RAM Size | 8 K |
| Supplier Device Package | 40-TQFN (6x6) |
| Voltage - Supply | 3.3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 0.00 | |
Description
General part information
MAXQ1850 Series
DeepCover®embedded security solutions cloak sensitive data under multiple layers of advanced physical security to provide the most secure key storage possible.The DeepCover Secure Microcontroller (MAXQ1850) is a low-power, 32-bit RISC device designed for electronic commerce, banking, and data security systems. It combines high-performance, single-cycle processing, sophisticated tamper-detection technology, and advanced cryptographic hardware to provide industry-leading data security and secret key protection.Physical security mechanisms include environmental sensors that detect out of range voltage or temperature conditions, responding with rapid zeroization of critical data. Four self-destruct inputs are provided for additional tamper response. An internal shield over the silicon provides protection from microprobe attacks. A high-speed internal ring oscillator is provided to thwart attacks that rely on controlling the clock rate of the chip. To protect data, the MAXQ1850 integrates several high-speed, analysis-resistant encryption engines. Algorithms supported in hardware include AES (128-, 192-, and 256-bit), DES, triple DES (2-key and 3-key), ECDSA (160-, 192-, and 256-bit keys), DSA, RSA (up to 2048 bits), SHA-1, SHA-224, and SHA-256. The advanced security features of the MAXQ1850 are designed to meet the stringent requirements of regulations such as ITSEC E3 High, FIPS 140-2 Level 3, and the Common Criteria certifications.The MAXQ1850 includes 256KB of flash memory and 8KB of secure, battery-backed data SRAM. Several communication protocols are supported with hardware engines, including ISO 7816 for smart card applications, USB (slave interface with four end-point buffers), an RS-232 universal synchronous/asynchronous receiver-transmitter (USART), an SPI interface (master or slave mode support), and up to 16 general-purpose I/O pins. Other peripherals supported on the MAXQ1850 include a true hardware random-number generator (RNG), a real-time clock (RTC), a programmable watchdog timer, and flexible 16-bit timers that support capture, compare, and pulse-width modulation (PWM) operations.Note: Designers must have following documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user's guides offer detailed information about device features and operation.MAXQ1850 IC data sheetMAXQ1850 revision-specific errata sheet (Click here for availability)MAXQ®Family User's GuideMAXQ Family User's Guide: MAXQ1850 Supplement (contact BU for availability)ApplicationsATM KeyboardsCertificate AuthenticationElectronic CommerceElectronic Signature GeneratorEMV® BankingPay-per-PlayPCI TerminalsPIN PadsSecure Access ControlSecure Data Storage