
CLVC1G374QDBVRQ1
ActiveAUTOMOTIVE CATALOG SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT
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CLVC1G374QDBVRQ1
ActiveAUTOMOTIVE CATALOG SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CLVC1G374QDBVRQ1 |
|---|---|
| Current - Output High, Low [custom] | 40 mA |
| Current - Output High, Low [custom] | 40 mA |
| Current - Quiescent (Iq) | 10 µA |
| Function | Standard |
| Grade | Automotive |
| Input Capacitance | 3 pF |
| Max Propagation Delay @ V, Max CL | 5 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | SOT-23-6 |
| Qualification | AEC-Q100 |
| Supplier Device Package | SOT-23-6 |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.49 | |
| 10 | $ 0.39 | |||
| 25 | $ 0.36 | |||
| 100 | $ 0.27 | |||
| 250 | $ 0.24 | |||
| 500 | $ 0.20 | |||
| 1000 | $ 0.15 | |||
| Digi-Reel® | 1 | $ 0.49 | ||
| 10 | $ 0.39 | |||
| 25 | $ 0.36 | |||
| 100 | $ 0.27 | |||
| 250 | $ 0.24 | |||
| 500 | $ 0.20 | |||
| 1000 | $ 0.15 | |||
| Tape & Reel (TR) | 3000 | $ 0.10 | ||
| Texas Instruments | LARGE T&R | 1 | $ 0.24 | |
| 100 | $ 0.16 | |||
| 250 | $ 0.13 | |||
| 1000 | $ 0.08 | |||
Description
General part information
SN74LVC1G374-Q1 Series
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input.
Documents
Technical documentation and resources