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Technical Specifications
Parameters and characteristics for this part
| Specification | TPIC6B595DWR |
|---|---|
| Function | Serial to Parallel, Serial |
| Logic Type | Shift Register |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Open Drain |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 20-SOIC |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.50 | |
| 10 | $ 1.34 | |||
| 25 | $ 1.28 | |||
| 100 | $ 1.05 | |||
| 250 | $ 0.98 | |||
| 500 | $ 0.87 | |||
| 1000 | $ 0.68 | |||
| Digi-Reel® | 1 | $ 1.50 | ||
| 10 | $ 1.34 | |||
| 25 | $ 1.28 | |||
| 100 | $ 1.05 | |||
| 250 | $ 0.98 | |||
| 500 | $ 0.87 | |||
| 1000 | $ 0.68 | |||
| Tape & Reel (TR) | 2000 | $ 0.64 | ||
| 6000 | $ 0.61 | |||
| 10000 | $ 0.58 | |||
| Texas Instruments | LARGE T&R | 1 | $ 1.11 | |
| 100 | $ 0.86 | |||
| 250 | $ 0.63 | |||
| 1000 | $ 0.45 | |||
Description
General part information
TPIC6B595 Series
The TPIC6B595 device is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium current or high-voltage loads.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively.
The storage register transfers data to the output buffer when shift-register clear ( SRCLR) is high. Write data and read data are valid only when RCK is low. When SRCLR is low, the input shift register is cleared. When output enable ( G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices.
Documents
Technical documentation and resources
