
MAX32570-MNJ+
ObsoleteLOW-POWER ARM CORTEX-M4 MICROCONTROLLER WITH CONTACTLESS RADIO FOR SECURE APPLICATIONS
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MAX32570-MNJ+
ObsoleteLOW-POWER ARM CORTEX-M4 MICROCONTROLLER WITH CONTACTLESS RADIO FOR SECURE APPLICATIONS
Technical Specifications
Parameters and characteristics for this part
| Specification | MAX32570-MNJ+ |
|---|---|
| Core Processor | ARM® Cortex®-M4F |
| Core Size | 32-Bit |
| Data Converters | A/D 1x10b Sigma-Delta |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 105 ░C |
| Operating Temperature [Min] | -40 C |
| Oscillator Type | Internal |
| Package / Case | 121-LFBGA |
| Peripherals | DMA, TRNG, WDT, AES, LCD |
| Program Memory Size | 1 MB |
| Program Memory Type | FLASH |
| RAM Size | 760 K |
| Speed | 150 MHz |
| Supplier Device Package | 121-CTBGA (8x8) |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 0.00 | |
Description
General part information
MAX32570 Series
The MAX32570 DeepCover®secure microcontroller provides an interoperable, secure, and cost-effective solution to build new generations of trusted devices. It can be used in single-chip applications such as PIN pads, mobile POS (MPOS), and secure card reader for PIN (SCRP), but also in dual-chip applications such as countertop and tablet POS. It includes all the essential functions to address those applications including a multi-protocol RF contactless controller and radio front-end, a dual smart card controller, a parallel camera interface, a magnetic stripe reader, a TFT controller and a secure keypad controller.The MAX32570 operates at 150MHz and is based on an Arm®Cortex®-M4 processor with FPU with 1MB flash, 760KB SRAM, 8KB OTP, 1KB of battery-backed AES self-encrypted nonvolatile SRAM (NVSRAM) and a 256-bit flip-flop based battery-backed key storage. The flash memory is split into 2 banks of 512KB to provide flexibility when programming over-the-air. Error correction coding (ECC) (single error correction double error detection) for flash, and SRAM provides extremely reliable code execution. The device embeds both secure public and private key cryptographic algorithms and a true random number generator (TRNG) compliant with SP-800-90A and SP-800-90B standards. It also features a number of security protections and detectors to enforce system integrity including a dynamic sensor controller, environmental sensors, and fault detectors.The device features five flexible power modes. Multiple SPI, UART, and I2C serial interfaces, as well as a QSPI, 1-Wire®master, a USB 2.0 High-Speed device and an optional 10/100 Ethernet MAC, allow for greater connectivity. Some device package variants offer flexible off-chip memory expansion that supports SD/SDHC, SDIO/eMMC cards, QSPI flash, and SRAM memories with eXecute In Place (XIP), encryption, and authentication. The device is available in a number of package variants, ranging from 121-pin BGA to 169-pin BGA, 0.65mm pitch packages.ApplicationsATM KeyboardsContact/Contactless PinpadsCountertop and Tablet POSPCI Mobile Payment Terminals (mPOS)Secure Card Reader for PIN (SCRP)
Documents
Technical documentation and resources