TPS65192RHDR
Active9-CHANNEL LEVEL SHIFTER FOR LCD DISPLAYS WITH GPM
Deep-Dive with AI
Search across all available documentation for this part.
TPS65192RHDR
Active9-CHANNEL LEVEL SHIFTER FOR LCD DISPLAYS WITH GPM
Technical Specifications
Parameters and characteristics for this part
| Specification | TPS65192RHDR |
|---|---|
| Applications | Video Display |
| Function | Shifter |
| Mounting Type | Surface Mount |
| Package / Case | 28-VFQFN Exposed Pad |
| Supplier Device Package | 28-VQFN (5x5) |
| Voltage - Supply [Max] | 38 V |
| Voltage - Supply [Min] | 12 VDC |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 2.68 | |
| Digi-Reel® | 1 | $ 2.68 | ||
| N/A | 0 | $ 1.42 | ||
| 549 | $ 1.42 | |||
| Tape & Reel (TR) | 3000 | $ 1.23 | ||
| 6000 | $ 1.18 | |||
| Texas Instruments | LARGE T&R | 1 | $ 1.82 | |
| 100 | $ 1.59 | |||
| 250 | $ 1.12 | |||
| 1000 | $ 0.90 | |||
Description
General part information
TPS65192 Series
The TPS65192 is a 9 channel level-shifter intended for use in LCD display applications such as TVs and monitors. The device converts the logic-level signals generated by the Timing Controller (T-CON) to the high-level signals used by the display panel.
The 9 level shifter channels are organized as two groups. Channels 1 through 7 are powered from VGH1and VGL, and channels 8 and 9 are powered from VGH2and VGL. Each level-shifter channel features low impedance output stages that achieve fast rise and fall times even when driving the capacitive loading typically present in LCD display applications.
Level shifter channels 1 through 6 support gate voltage shaping, which can be used to improve picture quality by reducing image sticking. Novel decoding logic enables a single flicker clock signal to control gate voltage shaping for all CLK channels without the need for synchronization. The device also supports the use of multiple flicker clocks. The rate of decay is set by an external resistor or resistor network connected to the RE pin.
Documents
Technical documentation and resources