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40-VQFN Exposed pad
Integrated Circuits (ICs)

DRV8304SRHAR

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Texas Instruments

40-V MAX 3-PHASE SMART GATE DRIVER WITH CURRENT SHUNT AMPLIFIER

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40-VQFN Exposed pad
Integrated Circuits (ICs)

DRV8304SRHAR

Active
Texas Instruments

40-V MAX 3-PHASE SMART GATE DRIVER WITH CURRENT SHUNT AMPLIFIER

Technical Specifications

Parameters and characteristics for this part

SpecificationDRV8304SRHAR
Channel Type3-Phase
Current - Peak Output (Source, Sink)150 mA, 300 mA
Driven ConfigurationHigh-Side, Low-Side
Gate TypeN-Channel MOSFET
Input TypeNon-Inverting
Logic Voltage - VIL, VIH [custom]1.5 V
Logic Voltage - VIL, VIH [custom]0.8 V
Mounting TypeSurface Mount
Number of Drivers3
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Package / Case40-VFQFN Exposed Pad
Rise / Fall Time (Typ) [custom]300 ns
Rise / Fall Time (Typ) [custom]150 ns
Supplier Device Package40-VQFN (6x6)
Voltage - Supply [Max]38 V
Voltage - Supply [Min]6 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 3.27
10$ 2.45
25$ 2.18
50$ 2.07
100$ 2.02
500$ 1.69
1000$ 1.58
Digi-Reel® 1$ 3.27
10$ 2.45
25$ 2.18
50$ 2.07
100$ 2.02
500$ 1.69
1000$ 1.58
Tape & Reel (TR) 2500$ 1.34
5000$ 1.30
7500$ 1.27
Texas InstrumentsLARGE T&R 1$ 2.05
100$ 1.70
250$ 1.22
1000$ 0.92

Description

General part information

DRV8304 Series

The DRV8304 device is an integrated gate driver for 3-phase brushless DC (BLDC) motors applications for 12-V and 24-V DC rails. These applications include field-oriented control (FOC), sinusoidal current control, and trapezoidal current control of BLDC motors. The device integrates three current-sense amplifiers (CSA) for sensing the phase currents of BLDC motors for optimum FOC and current-control system implementation. An AUTOCAL feature automatically calibrates the CSA offset error for accurate current sensing.

The device is based on smart gate-drive (SGD) architecture to eliminate the need of any external gate components (resistors and Zener diodes) while fully protecting the external FETs. The SGD architecture optimizes dead time to avoid any shoot-through conditions, provides flexibility in decreasing electromagnetic interference (EMI) by gate slew-rate control, and protects against any gate-short conditions through VGShand-shaking and dead time insertion. Strong pulldown current also prevents any dv/dt gate turnon.

Various PWM control modes (1x, 3x, 6x, and independent) are supported for simple interfacing to control circuits that can be powered by the 30-mA, 3.3-V internal regulator. These modes decrease the number of output peripherals of the controller for the specific motor-control requirements and provide flexibility of control. The device also has a 1x mode for sensored trapezoidal control of the BLDC motor by using the internal block-commutation table. The device can also be configured to drive multiple loads, such as solenoids, in independent mode.