Integrated Circuits (ICs)

S70KL1281DABHI023

Obsolete

INFINEON

IC PSRAM 128MBIT PAR 24FBGA

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Integrated Circuits (ICs)

S70KL1281DABHI023

Obsolete

INFINEON

IC PSRAM 128MBIT PAR 24FBGA

Deep-Dive with AI

DocumentsDatasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	S70KL1281DABHI023

Access Time	40 ns
Clock Frequency	100 MHz
Memory Format	PSRAM
Memory Interface	Parallel
Memory Organization	16M x 8
Memory Size	16 MB
Memory Type	Volatile
Mounting Type	Surface Mount
Operating Temperature [Max]	85 C
Operating Temperature [Min]	-40 ¯C
Package / Case	24-VBGA
Supplier Device Package	24-FBGA
Supplier Device Package [x]	6
Supplier Device Package [y]	8
Technology	PSRAM (Pseudo SRAM)
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2.7 V

S70KL1281 Series

Part	Package / Case	Memory Type	Memory Size	Mounting Type	Supplier Device Package [y]	Supplier Device Package	Supplier Device Package [x]	Memory Organization	Access Time	Memory Interface	Technology	Memory Format	Voltage - Supply [Max]	Voltage - Supply [Min]	Operating Temperature [Max]	Operating Temperature [Min]	Clock Frequency
INFINEON S70KL1281DABHI023	24-VBGA	Volatile	16 MB	Surface Mount	8	24-FBGA	6	16M x 8	40 ns	Parallel	PSRAM (Pseudo SRAM)	PSRAM	3.6 V	2.7 V	85 C	-40 ¯C	100 MHz
INFINEON S70KL1281DABHV020	24-VBGA	Volatile	16 MB	Surface Mount	8	24-FBGA	6	16M x 8	40 ns	Parallel	PSRAM (Pseudo SRAM)	PSRAM	3.6 V	2.7 V	105 °C	-40 °C	100 MHz
INFINEON S70KL1281DABHI020	24-VBGA	Volatile	16 MB	Surface Mount	8	24-FBGA	6	16M x 8	40 ns	Parallel	PSRAM (Pseudo SRAM)	PSRAM	3.6 V	2.7 V	85 C	-40 ¯C	100 MHz

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	N/A	0	$ 0.00

Description

General part information

S70KL1281 Series

The Cypress® HyperRAM™ device is a high-speed CMOS DRAM with a HyperBus interface. The 128 Mb version is a dual-die stack of 64 Mb devices. With refresh control logic, it resembles PSRAM to the host, eliminating the need for manual refresh operations. The host should manage transaction duration to accommodate internal refresh needs.

Documents

Technical documentation and resources