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MK2304-1 - Block Diagram
Integrated Circuits (ICs)

MK2304S-1LFT

Obsolete
Renesas Electronics Corporation

ZERO DELAY, LOW SKEW BUFFER

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MK2304-1 - Block Diagram
Integrated Circuits (ICs)

MK2304S-1LFT

Obsolete
Renesas Electronics Corporation

ZERO DELAY, LOW SKEW BUFFER

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationMK2304S-1LFT
Differential - Input:OutputFalse
Divider/MultiplierNo
Divider/MultiplierYes
Frequency - Max [Max]133 MHz
InputClock
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
OutputCMOS
Package / Case8-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
PLLTrue
Ratio - Input:Output1:4
Supplier Device Package8-SOIC
TypeZero Delay Buffer
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$

Description

General part information

MK2304-2 Series

The MK2304-2 is a low jitter, low skew, high performance Phase Lock Loop (PLL) based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter PLL techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The MK2304-2 includes a bank of two outputs running at 1/2X. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all 4 outputs. Compared to competitive CMOS devices, the MK2304-2 has the lowest jitter. The MK2304-2 PLL enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are tri-stated and the PLL is turned off, resulting in leass than 25 ?A of current draw. IDT manufactures the largest variety of clock generators and buffers and is the largest clock supplier in the world.

Documents

Technical documentation and resources