The DS1556 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) with an RTC alarm, watchdog timer, power-on reset, battery monitor, and 128k x 8 nonvolatile static RAM. User access to all registers within the DS1556 is accomplished with a byte-wide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for day of month and leap year are made automatically.The RTC registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is continuously updated, which occurs regardless of external registers settings to guarantee that accurate RTC information is always maintained.The DS1556 has interrupt (active-low IRQ/FT) and reset (active-low RST) outputs which can be used to control CPU activity. The active-low IRQ/FT interrupt output can be used to generate an external interrupt when the RTC register values match user programmed alarm values. The interrupt is always available while the device is powered from the system supply and can be programmed to occur when in the battery-backed state to serve as a system wake-up. Either the active-low IRQ/FT or active-low RST outputs can also be used as a CPU watchdog timer, CPU activity is monitored and an interrupt or reset output will be activated if the correct activity is not detected within programmed limits. The DS1556 power-on reset can be used to detect a system power down or failure and hold the CPU in a safe reset state until normal power returns and stabilizes; the active-low RST output is used for this function.The DS1556 also contains its own power-fail circuitry, which automatically deselects the device when the VCCsupply enters an out of tolerance condition. This feature provides a high degree of data security during unpredictable system operation brought on by low VCClevels.