74HC573D-Q100,118
ActiveLATCH, 74HC573, D TYPE TRANSPARENT, TRI STATE NON INVERTED, 26 NS, 7.8 MA, 20 PINS, SOIC
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74HC573D-Q100,118
ActiveLATCH, 74HC573, D TYPE TRANSPARENT, TRI STATE NON INVERTED, 26 NS, 7.8 MA, 20 PINS, SOIC
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Technical Specifications
Parameters and characteristics for this part
| Specification | 74HC573D-Q100,118 |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low [custom] | 7.8 mA |
| Current - Output High, Low [custom] | 7.8 mA |
| Delay Time - Propagation | 14 ns |
| Grade | Automotive |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Qualification | AEC-Q100 |
| Supplier Device Package | 20-SO |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.64 | |
| 10 | $ 0.56 | |||
| 25 | $ 0.53 | |||
| 100 | $ 0.43 | |||
| 250 | $ 0.40 | |||
| 500 | $ 0.34 | |||
| 1000 | $ 0.27 | |||
| Digi-Reel® | 1 | $ 0.64 | ||
| 10 | $ 0.56 | |||
| 25 | $ 0.53 | |||
| 100 | $ 0.43 | |||
| 250 | $ 0.40 | |||
| 500 | $ 0.34 | |||
| 1000 | $ 0.27 | |||
| Tape & Reel (TR) | 2000 | $ 0.25 | ||
| 6000 | $ 0.23 | |||
| 10000 | $ 0.22 | |||
Description
General part information
74HC573D-Q100 Series
The 74HC573-Q100; 74HCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Documents
Technical documentation and resources