Integrated Circuits (ICs)

CDCV857BIDGG

Obsolete

Texas Instruments

IC PLL CLOCK DRIVER 48TSSOP

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsDatasheet

Integrated Circuits (ICs)

CDCV857BIDGG

Obsolete

Texas Instruments

IC PLL CLOCK DRIVER 48TSSOP

Deep-Dive with AI

DocumentsDatasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	CDCV857BIDGG

Differential - Input:Output [custom]	True
Differential - Input:Output [custom]	True
Divider/Multiplier	False
Frequency - Max [Max]	200 MHz
Input	Clock
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	Clock
Package / Case	48-TFSOP
Package / Case	0.24 in
Package / Case [custom]	6.1 mm
PLL	Yes with Bypass
Ratio - Input:Output [custom]	1:10
Supplier Device Package	48-TSSOP
Type	PLL Clock Driver
Voltage - Supply [Max]	2.7 V
Voltage - Supply [Min]	2.3 V

CDCV857A Series

2.5-V SSTL-II phase-lock loop clock driver for double data-rate synchronous DRAM applications

Part	Mounting Type	Supplier Device Package	Input	Package / Case	Frequency - Max [Max]	Ratio - Input:Output [custom]	Number of Circuits	Voltage - Supply [Max]	Voltage - Supply [Min]	PLL	Operating Temperature [Min]	Operating Temperature [Max]	Output	Type	Package / Case	Package / Case [custom]
Texas Instruments CDCV857BGQLR	Surface Mount	56-BGA Microstar Junior (7x4.5)	Clock	56-VFBGA	200 MHz	1:10	1	2.7 V	2.3 V	Yes with Bypass	0 °C	85 °C	Clock	PLL Clock Driver
Texas Instruments CDCV857DGG	Surface Mount	48-TSSOP	Clock	48-TFSOP	200 MHz	1:10	1	2.7 V	2.3 V	Yes with Bypass	0 °C	85 °C	Clock	PLL Clock Driver	0.24 in	6.1 mm
Texas Instruments CDCV857BDGGR	Surface Mount	48-TSSOP	Clock	48-TFSOP	200 MHz	1:10	1	2.7 V	2.3 V	Yes with Bypass	0 °C	85 °C	Clock	PLL Clock Driver	0.24 in	6.1 mm
Texas Instruments CDCV857BIDGGR	Surface Mount	48-TSSOP	Clock	48-TFSOP	200 MHz	1:10	1	2.7 V	2.3 V	Yes with Bypass	-40 °C	85 °C	Clock	PLL Clock Driver	0.24 in	6.1 mm
Texas Instruments CDCV857AGQLR	Surface Mount	56-BGA Microstar Junior (7x4.5)	Clock	56-VFBGA	180 MHz	1:10	1	2.7 V	2.3 V	Yes with Bypass	0 °C	85 °C	Clock	PLL Clock Driver
Texas Instruments CDCV857BIDGG	Surface Mount	48-TSSOP	Clock	48-TFSOP	200 MHz	1:10	1	2.7 V	2.3 V	Yes with Bypass	-40 °C	85 °C	Clock	PLL Clock Driver	0.24 in	6.1 mm
Texas Instruments CDCV857DGGR	Surface Mount	48-TSSOP	Clock	48-TFSOP	200 MHz	1:10	1	2.7 V	2.3 V	Yes with Bypass	0 °C	85 °C	Clock	PLL Clock Driver	0.24 in	6.1 mm
Texas Instruments CDCV857ADGG	Surface Mount	48-TSSOP	Clock	48-TFSOP	180 MHz	1:10	1	2.7 V	2.3 V	Yes with Bypass	0 °C	85 °C	Clock	PLL Clock Driver	0.24 in	6.1 mm
Texas Instruments CDCV857BDGGRG4	Surface Mount	48-TSSOP	Clock	48-TFSOP	200 MHz	1:10	1	2.7 V	2.3 V	Yes with Bypass	0 °C	85 °C	Clock	PLL Clock Driver	0.24 in	6.1 mm
Texas Instruments CDCV857BDGG	Surface Mount	48-TSSOP	Clock	48-TFSOP	200 MHz	1:10	1	2.7 V	2.3 V	Yes with Bypass	0 °C	85 °C	Clock	PLL Clock Driver	0.24 in	6.1 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

CDCV857A Series

The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]\) and one differential pair of feedback clock output (FBOUT, FBOUT\). The clock outputs are controlled by the clock inputs (CLK, CLK\), the feedback clocks (FBIN, FBIN\), and the analog power input (AVDD). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and enables the outputs.

When AVDDis strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857A is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV857A is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857A is characterized for operation from 0°C to 85°C.

Documents

Technical documentation and resources