74AUP1G00GX,125
ActiveNAND GATE 1-ELEMENT 2-IN CMOS 5-PIN X2SON EP T/R
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74AUP1G00GX,125
ActiveNAND GATE 1-ELEMENT 2-IN CMOS 5-PIN X2SON EP T/R
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Technical Specifications
Parameters and characteristics for this part
| Specification | 74AUP1G00GX,125 |
|---|---|
| Current - Output High, Low [custom] | 4 mA |
| Current - Output High, Low [custom] | 4 mA |
| Current - Quiescent (Max) [Max] | 500 nA |
| Input Logic Level - High [Max] | 2 V |
| Input Logic Level - High [Min] | 1.6 V |
| Logic Type | NAND Gate |
| Max Propagation Delay @ V, Max CL | 6.5 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 C |
| Package / Case | 4-XFDFN Exposed Pad |
| Supplier Device Package | 5-X2SON |
| Supplier Device Package [x] | 0.8 |
| Supplier Device Package [y] | 0.8 |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 0.8 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
74AUP1G00GX Series
The 74AUP1G00 is a single 2-input NAND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCCrange from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Documents
Technical documentation and resources