The 74AHC595-Q100; 74AHCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous resetMRinput. A LOW onMRwill reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the registers. The 74AHCT595-Q100 features TTL compatible inputs. Both 74AHC595-Q100 and 74AHCT595-Q100 inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.