
SN74LVTH16835DGGR
Active3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS WITH 3-STATE OUTPUTS
Deep-Dive with AI
Search across all available documentation for this part.

SN74LVTH16835DGGR
Active3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS WITH 3-STATE OUTPUTS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LVTH16835DGGR |
|---|---|
| Current - Output High, Low [custom] | 64 mA |
| Current - Output High, Low [custom] | 32 mA |
| Logic Type | Universal Bus Driver |
| Mounting Type | Surface Mount |
| Number of Circuits | 18 Bit |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 6.1 mm |
| Package / Case | 0.24 in |
| Package / Case | 56-TFSOP |
| Supplier Device Package | 56-TSSOP |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 3.20 | |
| 10 | $ 2.88 | |||
| 25 | $ 2.72 | |||
| 100 | $ 2.36 | |||
| 250 | $ 2.23 | |||
| 500 | $ 2.01 | |||
| 1000 | $ 1.69 | |||
| Digi-Reel® | 1 | $ 3.20 | ||
| 10 | $ 2.88 | |||
| 25 | $ 2.72 | |||
| 100 | $ 2.36 | |||
| 250 | $ 2.23 | |||
| 500 | $ 2.01 | |||
| 1000 | $ 1.69 | |||
| Tape & Reel (TR) | 2000 | $ 1.61 | ||
| 6000 | $ 1.55 | |||
| Texas Instruments | LARGE T&R | 1 | $ 2.42 | |
| 100 | $ 2.12 | |||
| 250 | $ 1.48 | |||
| 1000 | $ 1.20 | |||
Description
General part information
SN74LVTH16835 Series
The 'LVTH16835 devices are 18-bit universal bus drivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
Data flow from A to Y is controlled by the output-enable (OE\) input. These devices operate in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of the clock. When OE\ is high, the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Documents
Technical documentation and resources