Zenode.ai Logo
Beta
144-FCBGA
Integrated Circuits (ICs)

ADC12SJ800AAVQ1

Active
Texas Instruments

AUTOMOTIVE SINGLE-CHANNEL, 12-BIT, 800-MSPS ADC WITH JESD204C INTERFACE

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsDatasheet
144-FCBGA
Integrated Circuits (ICs)

ADC12SJ800AAVQ1

Active
Texas Instruments

AUTOMOTIVE SINGLE-CHANNEL, 12-BIT, 800-MSPS ADC WITH JESD204C INTERFACE

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

SpecificationADC12SJ800AAVQ1
ArchitectureSAR
ConfigurationADC
Data InterfaceJESD204B Serial
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters4
Number of Bits12 bits
Number of Inputs8
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Package / CaseFCBGA, 144-FBGA
Ratio - S/H:ADC0:4
Reference TypeExternal
Sampling Rate (Per Second)800 M
Supplier Device Package144-FCBGA (10x10)
Voltage - Supply, Analog [Max]2 V, 1.15 V
Voltage - Supply, Analog [Min]1.8 V, 1.05 V
Voltage - Supply, Digital [Max]1.15 V
Voltage - Supply, Digital [Min]1.05 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 6$ 143.05
10$ 136.29
25$ 133.39
Texas InstrumentsJEDEC TRAY (5+1) 1$ 111.01
100$ 100.48
250$ 97.61
1000$ 95.70

Description

General part information

ADC12SJ800-Q1 Series

ADC12xJ800-Q1 is a family of quad, dual and single channel, 12-bit, 800MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC12xJ800-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

Documents

Technical documentation and resources