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20-QSOP
Integrated Circuits (ICs)

CY74FCT373CTQCTG4

Obsolete
Texas Instruments

IC D-TYPE TRANSP SGL 8:8 20SSOP

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20-QSOP
Integrated Circuits (ICs)

CY74FCT373CTQCTG4

Obsolete
Texas Instruments

IC D-TYPE TRANSP SGL 8:8 20SSOP

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCY74FCT373CTQCTG4
Circuit [custom]8
Circuit [custom]8
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]32 mA
Delay Time - Propagation2 ns
Independent Circuits1
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case20-SSOP
Package / Case [custom]0.154 in
Package / Case [custom]3.9 mm
Supplier Device Package20-SSOP
Voltage - Supply [Max]5.25 V
Voltage - Supply [Min]4.75 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

CY74FCT373T Series

The \x92FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.

These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.

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Technical documentation and resources

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