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ISL89367 Functional Diagram
Integrated Circuits (ICs)

ISL89367FRTAZ

Obsolete
Renesas Electronics Corporation

HIGH SPEED, DUAL CHANNEL, 6A, MOSFET DRIVER WITH PROGRAMMABLE RISING AND FALLING EDGE DELAY TIMERS

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ISL89367 Functional Diagram
Integrated Circuits (ICs)

ISL89367FRTAZ

Obsolete
Renesas Electronics Corporation

HIGH SPEED, DUAL CHANNEL, 6A, MOSFET DRIVER WITH PROGRAMMABLE RISING AND FALLING EDGE DELAY TIMERS

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationISL89367FRTAZ
Channel TypeIndependent
Current - Peak Output (Source, Sink) [custom]6 A
Current - Peak Output (Source, Sink) [custom]6 A
Driven ConfigurationLow-Side
Gate TypeN-Channel MOSFET
Input TypeNon-Inverting, Inverting
Mounting TypeSurface Mount
Number of Drivers2
Operating Temperature [Max]125 ¯C
Operating Temperature [Min]-40 °C
Package / Case16-WFDFN Exposed Pad
Rise / Fall Time (Typ) [custom]20 ns
Rise / Fall Time (Typ) [custom]20 ns
Voltage - Supply [Max]16 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

ISL89367 Series

The ISL89367 is a high-speed, 6A, 2 channel MOSFET driver optimized for synchronous rectifier applications. Internal timers can be programmed with resistors to delay the rising and/or falling edges of the outputs. Logically ANDed dual inputs are also provided. One input is for the PWM signal and the second can be used as an enable. A third control input is used to optionally invert the logical polarity of the driver outputs. Comparator like logical inputs allows this driver to be configured for any logic level from 3. 3V to 10 VDC. The precision logic thresholds provided by the comparators allow the use of external RC circuits to generate longer time delays than are possible with the internal timers. The comparators also allow the driver to be configured with a low output voltage that is negative relative to the logic ground if desired. This is useful for applications that require a negative turn-off gate drive voltage for driving FETs with logic thresholds. At high switching frequencies, these MOSFET drivers use very little bias current. Separate, non-overlapping drive circuits are used to drive each CMOS output FET to prevent shoot-thru currents in the output stage. The start-up sequence is design to prevent unexpected glitches when VDDis being turned on or turned off. When VDD~1V, an internal 10kΩ resistor between the output and ground helps to keep the output voltage low. When ~1V VDDUV, both outputs are driven low with very low resistance and the logic inputs are ignored. This insures that the driven FETs are off. When VDD> UVLO, and after a short delay, the outputs now respond to the logic inputs.

Documents

Technical documentation and resources