Specification	CDCLVD1216RGZR

Differential - Input:Output [custom]	True
Differential - Input:Output [custom]	True
Frequency - Max [Max]	800 MHz
Input	LVDS, LVCMOS, LVPECL
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	LVDS
Package / Case	48-VFQFN Exposed Pad
Ratio - Input:Output [custom]	16
Ratio - Input:Output [custom]	2
Supplier Device Package	48-VQFN (7x7)
Type	Fanout Buffer (Distribution), Multiplexer
Voltage - Supply [Max]	2.625 V
Voltage - Supply [Min]	2.375 V

CDCLVD1216 Series

Low jitter, 2-input selectable 1:16 universal-to-LVDS buffer

Part	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Output	Voltage - Supply [Min]	Voltage - Supply [Max]	Type	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Supplier Device Package	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Frequency - Max [Max]	Number of Circuits	Package / Case	Input
Texas Instruments CDCLVD1216RGZR	Surface Mount	85 °C	-40 °C	LVDS	2.375 V	2.625 V	Fanout Buffer (Distribution) Multiplexer			48-VQFN (7x7)	16	2	800 MHz	1	48-VFQFN Exposed Pad	LVCMOS LVDS LVPECL
Texas Instruments CDCLVD1216RGZT	Surface Mount	85 °C	-40 °C	LVDS	2.375 V	2.625 V	Fanout Buffer (Distribution) Multiplexer			48-VQFN (7x7)	16	2	800 MHz	1	48-VFQFN Exposed Pad	LVCMOS LVDS LVPECL

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	2500	$ 6.81
Texas Instruments	LARGE T&R	1	$ 8.74
		100	$ 7.64
		250	$ 5.89
		1000	$ 5.27

Description

General part information

CDCLVD1216 Series

The CDCLVD1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVDS clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVD1216 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1216 is specifically designed for driving 50 Ω transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open it disables the outputs (static). The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

Documents

Technical documentation and resources

2:16 Low Additive Jitter LVDS Buffer datasheet (Rev. B)

Data sheet