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Technical Specifications
Parameters and characteristics for this part
| Specification | TLV5627IPWG4 |
|---|---|
| Architecture | String DAC |
| Data Interface | SPI |
| Differential Output | False |
| INL/DNL (LSB) | 0.3 LSB, 0.03 LSB |
| Mounting Type | Surface Mount |
| Number of Bits | 8 |
| Number of D/A Converters | 4 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Voltage - Buffered |
| Package / Case | 16-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Reference Type | External |
| Settling Time | 18 µs |
| Supplier Device Package | 16-TSSOP |
| Voltage - Supply, Analog | 5 V |
| Voltage - Supply, Analog [Max] | 3.3 V |
| Voltage - Supply, Analog [Min] | 2.7 V |
| Voltage - Supply, Digital | 5 V |
| Voltage - Supply, Digital [Max] | 3.3 V |
| Voltage - Supply, Digital [Min] | 2.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 90 | $ 5.78 | |
Description
General part information
TLV5627 Series
The TLV5627 is a four channel, 8-bit voltage output digital-to-analog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5627 is programmed with a 16-bit serial word comprised of a DAC address, individual DAC control bits, and an 8-bit DAC value.
The device has provision for two supplies: one digital supply for the serial interface (via pins DVDDand DGND), and one for the DACs, reference buffers and output buffers (via pins AVDDand AGND). Each supply is independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins DVDDand DGND), with the DACs operating on a 5-V supply. The digital and analog supplies can be tied together.
The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode make it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow DACs A and B to have a different reference voltage than DACs C and D.
Documents
Technical documentation and resources
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