74LVC273D-Q100J
ActiveOCTAL D-TYPE FLIP-FLOP WITH RESET; POSITIVE-EDGE TRIGGER
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74LVC273D-Q100J
ActiveOCTAL D-TYPE FLIP-FLOP WITH RESET; POSITIVE-EDGE TRIGGER
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Technical Specifications
Parameters and characteristics for this part
| Specification | 74LVC273D-Q100J |
|---|---|
| Current - Output High, Low [custom] | 24 mA |
| Current - Output High, Low [custom] | 24 mA |
| Current - Quiescent (Iq) | 10 µA |
| Grade | Automotive |
| Input Capacitance | 5 pF |
| Max Propagation Delay @ V, Max CL | 8.2 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element [custom] | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Non-Inverted |
| Package / Case | 20-SOIC (0.295", 7.50mm Width) |
| Qualification | AEC-Q100 |
| Supplier Device Package | 20-SO |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 0.33 | |
Description
General part information
74LVC273D-Q100 Series
The 74LVC273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW onMRforces the outputs LOW independently of clock and data inputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Documents
Technical documentation and resources