74HCT107D,653
ActiveFLIP FLOP, 74HCT107, JK, 16 NS, 73 MHZ, 4 MA, 14 PINS, SOIC
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74HCT107D,653
ActiveFLIP FLOP, 74HCT107, JK, 16 NS, 73 MHZ, 4 MA, 14 PINS, SOIC
Technical Specifications
Parameters and characteristics for this part
| Specification | 74HCT107D,653 |
|---|---|
| Clock Frequency | 66 MHz |
| Current - Output High, Low [custom] | 4 mA |
| Current - Output High, Low [custom] | 4 mA |
| Current - Quiescent (Iq) | 4 çA |
| Function | Reset |
| Input Capacitance | 3.5 pF |
| Max Propagation Delay @ V, Max CL | 36 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Complementary |
| Package / Case | 3.9 mm, 0.154 in |
| Package / Case | 14-SOIC |
| Supplier Device Package | 14-SO |
| Trigger Type | Negative Edge |
| Type | JK Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 4758 | $ 0.60 | |
Description
General part information
74HCT107D Series
The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q andQoutputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Documents
Technical documentation and resources